LFSR Sequence Generator

Generate a pseudo-random bit stream from a Linear Feedback Shift Register — the engine behind CRC checksums, PN sequences, spread-spectrum scramblers and hardware PRNGs. Configure the register width, tap positions and a non-zero seed; the tool produces the output sequence and empirically determines the period by simulation, flagging maximal-length taps (period 2ⁿ−1). Pure integer arithmetic, in your browser.

Quick presets (maximal-length)

Taps (comma list)

Seed (hex)

Output bits to generate

Taps are 1-indexed from the input (left) end of the register; the seed's most-significant bit is the leftmost cell. This matches the standard maximal-length tap tables.

Output sequence

First 12 internal states (left → right)